Dmitry Ponomarev
Dmitry Ponomarev
Professor of Computer Science, Binghamton University
Verified email at - Homepage
Cited by
Cited by
Jump over ASLR: Attacking branch predictors to bypass ASLR
D Evtyushkin, D Ponomarev, N Abu-Ghazaleh
2016 49th Annual IEEE/ACM International Symposium on Microarchitecture …, 2016
Branchscope: A new side-channel attack on directional branch predictor
D Evtyushkin, R Riley, NCSEECE Abu-Ghazaleh, D Ponomarev
ACM SIGPLAN Notices 53 (2), 693-707, 2018
Non-monopolizable caches: Low-complexity mitigation of cache side channel attacks
L Domnitser, A Jaleel, J Loew, N Abu-Ghazaleh, D Ponomarev
ACM Transactions on Architecture and Code Optimization (TACO) 8 (4), 1-21, 2012
Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources
D Ponomarev, G Kucuk, K Ghose
Proceedings. 34th ACM/IEEE International Symposium on Microarchitecture …, 2001
Malware-aware processors: A framework for efficient online malware detection
M Ozsoy, C Donovick, I Gorelik, N Abu-Ghazaleh, D Ponomarev
2015 IEEE 21st International Symposium on High Performance Computer …, 2015
A high-resolution side-channel attack on last-level cache
M Kayaalp, N Abu-Ghazaleh, D Ponomarev, A Jaleel
Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016
Safespec: Banishing the spectre of a meltdown with leakage-free speculation
KN Khasawneh, EM Koruyeh, C Song, D Evtyushkin, D Ponomarev, ...
2019 56th ACM/IEEE Design Automation Conference (DAC), 1-6, 2019
Branch regulation: Low-overhead protection from code reuse attacks
M Kayaalp, M Ozsoy, N Abu-Ghazaleh, D Ponomarev
ACM SIGARCH Computer Architecture News 40 (3), 94-105, 2012
Register packing: Exploiting narrow-width operands for reducing register file pressure
O Ergin, D Balkan, K Ghose, D Ponomarev
37th International Symposium on Microarchitecture (MICRO-37'04), 304-315, 2004
Iso-x: A flexible architecture for hardware-managed isolated execution
D Evtyushkin, J Elwell, M Ozsoy, D Ponomarev, NA Ghazaleh, R Riley
2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, 190-202, 2014
Ensemble learning for low-level hardware-supported malware detection
KN Khasawneh, M Ozsoy, C Donovick, N Abu-Ghazaleh, D Ponomarev
International Symposium on Recent Advances in Intrusion Detection, 3-25, 2015
M-sim: a flexible, multithreaded architectural simulation environment
J Sharkey, D Ponomarev, K Ghose
Techenical report, Department of Computer Science, State University of New …, 2005
Hardware-based malware detection using low-level architectural features
M Ozsoy, KN Khasawneh, C Donovick, I Gorelik, N Abu-Ghazaleh, ...
IEEE Transactions on Computers 65 (11), 3332-3344, 2016
Covert channels through random number generator: Mechanisms, capacity estimation and mitigations
D Evtyushkin, D Ponomarev
Proceedings of the 2016 ACM SIGSAC conference on computer and communications …, 2016
Understanding and mitigating covert channels through branch predictors
D Evtyushkin, D Ponomarev, N Abu-Ghazaleh
ACM Transactions on Architecture and Code Optimization (TACO) 13 (1), 1-23, 2016
Increasing processor performance through early register release
O Ergin, D Balkan, D Ponomarev, K Ghose
IEEE International Conference on Computer Design: VLSI in Computers and …, 2004
SCRAP: Architecture for signature-based protection from code reuse attacks
M Kayaalp, T Schmitt, J Nomani, D Ponomarev, N Abu-Ghazaleh
2013 IEEE 19th International Symposium on High Performance Computer …, 2013
Ric: Relaxed inclusion caches for mitigating llc side-channel attacks
M Kayaalp, KN Khasawneh, HA Esfeden, J Elwell, N Abu-Ghazaleh, ...
Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017
RHMD: Evasion-resilient hardware malware detectors
KN Khasawneh, N Abu-Ghazaleh, D Ponomarev, L Yu
Proceedings of the 50th Annual IEEE/ACM international symposium on …, 2017
Optimization of parallel discrete event simulator for multi-core systems
D Jagtap, N Abu-Ghazaleh, D Ponomarev
2012 IEEE 26th International Parallel and Distributed Processing Symposium …, 2012
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