Donghoon Yoo
Cited by
Cited by
Privacy-preserving machine learning with fully homomorphic encryption for deep neural network
JW Lee, HC Kang, Y Lee, W Choi, J Eom, M Deryabin, E Lee, J Lee, ...
iEEE Access 10, 30039-30054, 2022
Efficient FHEW bootstrapping with small evaluation keys, and applications to threshold homomorphic encryption
Y Lee, D Micciancio, A Kim, R Choi, M Deryabin, J Eom, D Yoo
Annual International Conference on the Theory and Applications of …, 2023
Processor including a cache and a scratch pad memory and memory control method thereof
IH Park, RYU Soojung, D Yoo, DK Suh, KIM Jeongwook, CK Jang
US Patent 9,015,451, 2015
General bootstrapping approach for RLWE-based homomorphic encryption
A Kim, M Deryabin, J Eom, R Choi, Y Lee, W Ghang, D Yoo
IEEE Transactions on Computers, 2023
Method, medium, and apparatus with interrupt handling in a reconfigurable array
KS Yim, JW Kim, SJ Ryu, JK Park, JJ Yoo, D Yoo, CS Im, JD Lee, HS Kim
US Patent 7,836,291, 2010
Processor, apparatus, and method for memory management
B Egger, D Yoo
US Patent App. 13/216,852, 2012
TQSIM: A fast cycle-approximate processor simulator based on QEMU
S Kang, D Yoo, S Ha
Journal of Systems Architecture 66, 33-47, 2016
Instruction compressing apparatus and method
T Jin, D Yoo, B Egger, WS Kim, JS Lee, SH Kim, HJ Ahn
US Patent App. 12/912,533, 2011
Multi-core processor and method of controlling the same using revisable translation tables
YOO Donghoon, B Egger
US Patent 10,713,095, 2020
Profiler for optimizing processor architecture and application
D Yoo, S Ryu, J Kim, H Kim, HS Kim
US Patent 8,490,066, 2013
Medha: Microcoded hardware accelerator for computing on encrypted data
AC Mert, S Kwon, Y Shin, D Yoo, Y Lee, SS Roy
arXiv preprint arXiv:2210.05476, 2022
Scc based modulo scheduling for coarse-grained reconfigurable processors
W Kim, D Yoo, H Park, M Ahn
2012 International Conference on Field-Programmable Technology, 321-328, 2012
Area-efficient number theoretic transform architecture for homomorphic encryption
P Duong-Ngoc, S Kwon, D Yoo, H Lee
IEEE Transactions on Circuits and Systems I: Regular Papers 70 (3), 1270-1283, 2022
Method and apparatus for interrupt handling during loop processing in reconfigurable coarse grained array
SJ Ryu, JW Kim, D Yoo, HS Kim
US Patent 7,529,917, 2009
Operation net system: A formal design representation model for high-level synthesis of asynchronous systems based on transformations
DH Yoo, DI Lee, JA Lee
International Conference on Application and Theory of Petri Nets, 435-453, 2004
Accelerator for computing on encrypted data
SS Roy, AC Mert, S Kwon, Y Shin, D Yoo
Cryptology ePrint Archive, 2021
Benzene: An energy-efficient distributed hybrid cache architecture for manycore systems
N Kim, J Ahn, K Choi, D Sanchez, D Yoo, S Ryu
ACM Transactions on Architecture and Code Optimization (TACO) 15 (1), 1-23, 2018
Processing device and a swizzle pattern generator
M Chung, W Seo, HY Kim, S Ryu, D Yoo, JS Lee, Y Cho, CM Kim, SH Jin
US Patent App. 13/618,309, 2013
An instruction-scheduling-aware data partitioning technique for coarse-grained reconfigurable architectures
C Jang, J Kim, J Lee, HS Kim, DH Yoo, S Kim, HS Kim, S Ryu
Proceedings of the 2011 SIGPLAN/SIGBED conference on Languages, compilers …, 2011
Cache control device for prefetching using pattern analysis processor and prefetch instruction and prefetching method using cache control device
KIM Jun-Kyoung, D Yoo, J Kim, S Ryu
US Patent 9,886,384, 2018
The system can't perform the operation now. Try again later.
Articles 1–20