| Comparative Evaluation of Spin-Transfer-Torque and Magnetoelectric Random Access Memory S Wang, H Lee, F Ebrahimi, PK Amiri, KL Wang, P Gupta IEEE Journal on Emerging and Selected Topics in Circuits and Systems 6 (2 …, 2016 | 121 | 2016 |
| Write Error Rate and Read Disturbance in Electric-Field-Controlled MRAM C Grezes, H Lee, A Lee, S Wang, F Ebrahimi, X Li, K Wong, JA Katine, ... IEEE Magnetics Letters 8, 2016 | 60 | 2016 |
| Analysis and compact modeling of magnetic tunnel junctions utilizing voltage-controlled magnetic anisotropy H Lee, A Lee, S Wang, F Ebrahimi, P Gupta, PK Amiri, KL Wang IEEE Transactions on Magnetics 54 (4), 1-9, 2018 | 37 | 2018 |
| Evaluation of digital circuit-level variability in inversion-mode and junctionless FinFET technologies S Wang, G Leung, A Pan, CO Chui, P Gupta IEEE transactions on electron devices 60 (7), 2186-2193, 2013 | 34 | 2013 |
| PROCEED: A Pareto Optimization-Based Circuit-Level Evaluator for Emerging Devices S Wang, A Pan, CO Chui, P Gupta IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (1), 192 …, 2015 | 25 | 2015 |
| Proceed: A pareto optimization-based circuit-level evaluator for emerging devices S Wang, A Pan, CO Chui, P Gupta 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 818 …, 2014 | 25 | 2014 |
| MEMRES: A Fast Memory System Reliability Simulator S Wang, HC Hu, H Zheng, P Gupta IEEE Transactions on Reliability 65 (4), 1783-1797, 2016 | 24 | 2016 |
| MEMRES: A Fast Memory System Reliability Simulator S Wang, HC Hu, H Zheng, P Gupta The 11th IEEE Workshop on Silicon Errors in Logic System Effects (SELSE), 2015 | 24 | 2015 |
| Hybrid VC-MTJ/CMOS Non-volatile Stochastic Logic for Efficient Computing S Wang, S Pal, T Li, A Pan, C Grezes, PK Amiri, KL Wang, P Gupta Design, Automation & Test in Europe Conference (DATE), 1438-1443, 2017 | 22 | 2017 |
| A word line pulse circuit technique for reliable magnetoelectric random access memory H Lee, A Lee, S Wang, F Ebrahimi, P Gupta, PK Amiri, KL Wang IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (7 …, 2017 | 21 | 2017 |
| Tunneling negative differential resistance-assisted STT-RAM for efficient read and write operations S Wang, A Pan, CO Chui, P Gupta IEEE Transactions on Electron Devices 64 (1), 121-129, 2016 | 21 | 2016 |
| MTJ variation monitor-assisted adaptive MRAM write S Wang, H Lee, C Grezes, P Khalili, KL Wang, P Gupta 53rd Annual Design Automation Conference (DAC), 169, 2016 | 20 | 2016 |
| A Source Line Sensing (SLS) Scheme in Magnetoelectric Random Access Memory (MeRAM) for Reducing Read Disturbance and Improving Sensing Margin H Lee, C Grezes, S Wang, F Ebrahimi, P Khalili, P Gupta, K Wang IEEE Magnetic Letters, 2016 | 17* | 2016 |
| Design of ultracompact content addressable memory exploiting 1T-1MTJ cell C Zhuo, Z Yang, K Ni, M Imani, Y Luo, S Wang, D Zhang, X Yin IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2022 | 15 | 2022 |
| Gate underlap design for short channel effects control in cylindrical gate-all-around MOSFETs based on an analytical model L Zhang, S Wang, C Ma, J He, C Xu, Y Ma, Y Ye, H Liang, Q Chen, ... IETE Technical Review 29 (1), 29-35, 2012 | 13 | 2012 |
| SSM-CIM: An Efficient CIM Macro Featuring Single-Step Multi-bit MAC Computation for CNN Edge Inference H Zhang, S He, X Lu, X Guo, S Wang, Y Du, L Du IEEE Transactions on Circuits and Systems I: Regular Papers, 2023 | 11 | 2023 |
| Adaptive MRAM write and read with MTJ variation monitor S Wang, H Lee, C Grezes, PK Amiri, KL Wang, P Gupta IEEE Transactions on Emerging Topics in Computing 9 (1), 402-413, 2018 | 10 | 2018 |
| Assessing Benefits of a Buried Interconnect Layer in Digital Designs L Zhu, Y Badr, S Wang, S Iyer, P Gupta IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 9 | 2017 |
| Leveraging NMOS Negative Differential Resistance for Low Power, High Reliability Magnetic Memory S Wang, A Pan, C Grezes, P Amiri, CO Chui, P Gupta IEEE Transactions on Electronic Devices 64 (10), 4084 - 4090, 2017 | 8 | 2017 |
| An Evaluation Framework for Nanotransfer Printing-Based Feature-Level Heterogeneous Integration in VLSI Circuits G Leung, S Wang, A Pan, P Gupta, CO Chui IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (5 …, 2015 | 6 | 2015 |
PUNEET GUPTAUCLA Electrical and Computer EngineeringVerified email at g.ucla.edu
