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Jérémy Postel-Pellerin
Jérémy Postel-Pellerin
IM2NP
Verified email at im2np.fr
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Year
True random number generator integration in a resistive RAM memory array using input current limitation
H Aziza, J Postel-Pellerin, H Bazzi, P Canet, M Moreau, V Della Marca, ...
IEEE Transactions on Nanotechnology 19, 214-222, 2020
372020
ReRAM ON/OFF resistance ratio degradation due to line resistance combined with device variability in 28nm FDSOI technology
H Aziza, P Canet, J Postel-Pellerin, M Moreau, JM Portal, M Bocquet
2017 Joint International EUROSOI Workshop and International Conference on …, 2017
172017
Push the flash floating gate memories toward the future low energy application
V Della Marca, G Just, A Regnier, JL Ogier, R Simola, S Niel, ...
Solid-State Electronics 79, 210-217, 2013
172013
True random number generation exploiting SET voltage variability in resistive RAM memory arrays
J Postel-Pellerin, H Bazzi, H Aziza, P Canet, M Moreau, V Della Marca, ...
2019 19th Non-Volatile Memory Technology Symposium (NVMTS), 1-5, 2019
152019
Impact of endurance degradation on the programming efficiency and the energy consumption of NOR flash memories
V Della Marca, J Postel-Pellerin, G Just, P Canet, JL Ogier
Microelectronics Reliability 54 (9-10), 2262-2265, 2014
152014
Extraction of 3D parasitic capacitances in 90 nm and 22 nm NAND flash memories
J Postel-Pellerin, F Lalande, P Canet, R Bouchakour, F Jeuland, ...
Microelectronics Reliability 49 (9-11), 1056-1059, 2009
102009
Integrated reliability in EEPROM nonvolatile memory cell design
P Canet, F Lalande, J Razafindramora, V Bouquet, J Postel-Pellerin, ...
Proceedings. 2004 IEEE Computational Systems Bioinformatics Conference, 66-69, 2004
102004
Impact of resistive paths on NVM array reliability: Application to Flash & ReRAM memories
P Canet, J Postel-Pellerin, H Aziza
Microelectronics Reliability 64, 36-41, 2016
82016
Modeling charge variation during data retention of MLC Flash memories
J Postel-Pellerin, F Lalande, P Canet, R Bouchakour, F Jeuland, ...
Microelectronics Reliability 49 (9-11), 1060-1063, 2009
82009
An augmented OxRAM synapse for spiking neural network (SNN) circuits
H Aziza, H Bazzi, J Postel-Pellerin, P Canet, M Moreau, A Harb
2019 14th International Conference on Design & Technology of Integrated …, 2019
72019
Impact of a laser pulse on a stt-mram bitcell: Security and reliability issues
M Kharbouche-Harrari, J Postel-Pellerin, G Di Pendina, R Wacquez, ...
2018 IEEE 24th International Symposium on On-Line Testing And Robust System …, 2018
72018
Suppressing the memory state of floating gate transistors with repeated femtosecond laser backside irradiations
M Chambonneau, S Souiki-Figuigui, P Chiquet, V Della Marca, ...
Applied Physics Letters 110 (16), 2017
72017
Data retention under gate stress on a NVM array
R Djenadi, G Micolau, J Postel-Pellerin, P Chiquet, R Laffont, JL Ogier, ...
Solid-state electronics 78, 80-86, 2012
72012
Charge loss activation during non-volatiles memory data retention
J Postel-Pellerin, G Micolau, P Chiquet, R Laffont, F Lalande, JL Ogier
CAS 2012 (International Semiconductor Conference) 2, 377-380, 2012
62012
An evaluation of the extrinsic cells number in a memory array using cross-correlation products and deconvolution: an instance of a microelectronics experimental inverse problem
G Micolau, J Postel-Pellerin, R Laffont, F Lalande, C Le Roux, JL Ogier
Inverse problems in science and engineering 19 (8), 1043-1062, 2011
62011
Leakage paths identification in NVM using biased data retention
J Postel-Pellerin, R Laffont, G Micolau, F Lalande, A Régnier, B Bouteille
Microelectronics Reliability 50 (9-11), 1474-1478, 2010
62010
A Full TCAD simulation and 3D parasitic capacitances extraction in 90nm NAND Flash memories
J Postel-Pellerin, P Canet, F Lalande, R Bouchakour, F Jeuland, ...
2008 9th Annual Non-Volatile Memory Technology Symposium (NVMTS), 1-4, 2008
62008
Experimental study to push the Flash floating gate memories toward low energy applications
V Della Marca, A Regnier, JL Ogier, R Simola, S Niel, J Postel-Pellerin, ...
2011 International Semiconductor Device Research Symposium (ISDRS), 1-2, 2011
52011
Energy consumption optimization in nonvolatile silicon nanocrystal memories
V Della Marca, J Amouroux, J Delalleau, L Lopez, JL Ogier, ...
CAS 2011 Proceedings (2011 International Semiconductor Conference) 2, 339-342, 2011
52011
Impact of stress on Fowler–Nordheim parameters effects on EEPROM threshold voltage
J Postel-Pellerin, F Lalande, P Canet, S Boutahar, R Bouchakour, ...
Journal of non-crystalline solids 353 (5-7), 610-614, 2007
52007
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Articles 1–20