| Planar Fully depleted SOI technology: A Powerful architecture for the 20nm node and beyond O Faynot, F Andrieu, O Weber, C Fenouillet-Béranger, P Perreau, ... 2010 International Electron Devices Meeting, 3.2. 1-3.2. 4, 2010 | 323 | 2010 |
| Multi-UTBB FDSOI Device Architectures for Low-Power CMOS Circuit JP Noel, O Thomas, MA Jaud, O Weber, T Poiroux, C Fenouillet-Beranger, ... IEEE Transactions on Electron Devices 58 (8), 2473-2482, 2011 | 235 | 2011 |
| Can we go towards true 3-D architectures? PE Gaillardon, H Ben-Jamaa, PH Morel, JP Noël, F Clermidy, I O'Connor Proceedings of the 48th Design Automation Conference, 282-283, 2011 | 233 | 2011 |
| Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond F Andrieu, O Weber, J Mazurier, O Thomas, JP Noel, ... 2010 Symposium on VLSI Technology, 57-58, 2010 | 116 | 2010 |
| Efficient multi-VTFDSOI technology with UTBOX for low power circuit design C Fenouillet-Beranger, O Thomas, P Perreau, JP Noel, A Bajolet, ... 2010 Symposium on VLSI Technology, 65-66, 2010 | 88 | 2010 |
| Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology P Flatresse, B Giraud, JP Noel, B Pelloux-Prayer, F Giner, DK Arora, ... 2013 IEEE International Solid-State Circuits Conference Digest of Technical …, 2013 | 87 | 2013 |
| Experimental investigation of 4-kb RRAM arrays programming conditions suitable for TCAM A Grossi, E Vianello, C Zambelli, P Royer, JP Noel, B Giraud, L Perniola, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (12 …, 2018 | 74 | 2018 |
| A 460 mhz at 397 mv, 2.6 ghz at 1.3 v, 32 bits vliw dsp embedding f max tracking E Beigne, A Valentian, I Miro-Panades, R Wilson, P Flatresse, F Abouzeid, ... IEEE Journal of Solid-State Circuits 50 (1), 125-136, 2014 | 62 | 2014 |
| Hybrid FDSOI/Bulk high-k/Metal gate platform for Low Power (LP) multimedia technology C Fenouillet-Beranger, P Perreau, L Pham-Nguyen, S Denorme, ... 2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009 | 61 | 2009 |
| UTBB FDSOI transistors with dual STI for a multi-Vt strategy at 20nm node and below L Grenouillet, M Vinet, J Gimbert, B Giraud, JP Noel, Q Liu, P Khare, ... 2012 International Electron Devices Meeting, 3.6. 1-3.6. 4, 2012 | 60 | 2012 |
| A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking R Wilson, E Beigne, P Flatresse, A Valentian, F Abouzeid, T Benoist, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 53 | 2014 |
| DRC2: Dynamically Reconfigurable Computing Circuit based on memory architecture KC Akyel, HP Charles, J Mottin, B Giraud, G Suraci, S Thuries, JP Noel 2016 IEEE International Conference on Rebooting Computing (ICRC), 1-8, 2016 | 51 | 2016 |
| Work-function engineering in gate first technology for multi-VTdual-gate FDSOI CMOS on UTBOX O Weber, F Andrieu, J Mazurier, M Casse, X Garros, C Leroux, F Martin, ... 2010 International Electron Devices Meeting, 3.4. 1-3.4. 4, 2010 | 51 | 2010 |
| Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs E Beigné, A Valentian, B Giraud, O Thomas, T Benoist, Y Thonnart, ... 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 613-618, 2013 | 39 | 2013 |
| SamurAI: A 1.7 MOPS-36GOPS adaptive versatile IoT node with 15,000× peak-to-idle power reduction, 207ns wake-up time and 1.3 TOPS/W ML efficiency I Miro-Panades, B Tain, JF Christmann, D Coriat, R Lemaire, C Jany, ... 2020 IEEE Symposium on VLSI Circuits, 1-2, 2020 | 37 | 2020 |
| A simple and efficient concept for setting up multi-VT devices in thin BOx fully-depleted SOI technology JP Noel, O Thomas, C Fenouillet-Beranger, MA Jaud, P Scheiblin, ... 2009 Proceedings of the European Solid State Device Research Conference, 137-140, 2009 | 34 | 2009 |
| Memory circuit capable of implementing calculation operations JP Noel, KC Akyel US Patent 10,043,581, 2018 | 33 | 2018 |
| SneakPath compensation circuit for programming and read operations in RRAM-based CrossPoint architectures A Levisse, B Giraud, JP Noel, M Moreau, JM Portal 2015 15th Non-Volatile Memory Technology Symposium (NVMTS), 1-4, 2015 | 33 | 2015 |
| Memory sizing of a scalable SRAM in-memory computing tile based architecture R Gauchi, M Kooli, P Vivet, JP Noel, E Beigné, S Mitra, HP Charles 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration …, 2019 | 32 | 2019 |
| Novel 1T2R1T RRAM-based ternary content addressable memory for large scale pattern recognition DRB Ly, JP Noel, B Giraud, P Royer, E Esmanhotto, N Castellani, ... 2019 IEEE International Electron Devices Meeting (IEDM), 35.5. 1-35.5. 4, 2019 | 31 | 2019 |
