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Evelina Forno
Evelina Forno
Verified email at polito.it
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Cited by
Year
Braille letter reading: A benchmark for spatio-temporal pattern recognition on neuromorphic hardware
SF Müller-Cleve, V Fra, L Khacef, A Pequeño-Zurro, D Klepatsch, E Forno, ...
Frontiers in Neuroscience 16, 951164, 2022
272022
Human activity recognition: suitability of a neuromorphic approach for on-edge AIoT applications
V Fra, E Forno, R Pignari, TC Stewart, E Macii, G Urgese
Neuromorphic Computing and Engineering 2 (1), 014006, 2022
152022
Spike encoding techniques for IoT time-varying signals benchmarked on a neuromorphic classification task
E Forno, V Fra, R Pignari, E Macii, G Urgese
Frontiers in Neuroscience 16, 999029, 2022
132022
A parallel hardware architecture for quantum annealing algorithm acceleration
E Forno, A Acquaviva, Y Kobayashi, E Macii, G Urgese
2018 IFIP/IEEE International Conference on Very Large Scale Integration …, 2018
82018
Techniques for improving localization applications running on low-cost IoT devices
E Forno, S Moio, M Schenatti, E Macii, G Urgese
2020 AEIT International Conference of Electrical and Electronic Technologies …, 2020
72020
Benchmarking a many-core neuromorphic platform with an MPI-based dna sequence matching algorithm
G Urgese, F Barchi, E Parisi, E Forno, A Acquaviva, E Macii
Electronics 8 (11), 1342, 2019
52019
Configuring an embedded neuromorphic coprocessor using a risc-v chip for enabling edge computing applications
E Forno, A Spitale, E Macii, G Urgese
2021 IEEE 14th International Symposium on Embedded Multicore/Many-core …, 2021
42021
Pagerank implemented with the mpi paradigm running on a many-core neuromorphic platform
E Forno, A Salvato, E Macii, G Urgese
Journal of Low Power Electronics and Applications 11 (2), 25, 2021
42021
Interfacing a Neuromorphic Coprocessor with a RISC-V Architecture
A Spitale
Politecnico di Torino, 2021
12021
Study and implementation of new computational paradigms exploiting neuromorphic hardware architectures
E Forno
Politecnico di Torino, 2023
2023
Constraint Satisfaction Problems solution through Spiking Neural Networks with improved reliability: the case of Sudoku puzzles
R Pignari, V Fra, E Forno, E Macii, G Urgese
Frontiers in Neuroscience–Neural Technologies, 2023
2023
Impact of Encoding Techniques on the Classification of Raw Time-Variant Signals with Spiking Neural Networks
R Pignari
Politecnico di Torino, 2022
2022
Smart Traffic Light Control on Edge in IOT-Regulated Intersections
E Forno, V Fra, MD Arisoy, C Zhou, AS Ferraris, E Macii, G Urgese
Titolo volume non avvalorato, 23-28, 2022
2022
A graph oriented approach for implementing the MPI multicast communicator on a many-core GALS platform
A Salvato
Politecnico di Torino, 2020
2020
Design of a parallel hardware architecture for Quantum Annealing Algorithm acceleration
E Forno
Politecnico di Torino, 2018
2018
Design of a parallel hardware architecture for Quantum Annealing Algorithm acceleration
A Acquaviva, PDG Urgese, E Forno
2018
2021 IEEE 14th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)| 978-1-6654-3860-5/21/$31.00© 2021 IEEE| DOI: 10.1109/MCSOC51149. 2021.00067
O Abboud, FA Abir, T Ahmed, H Amano, Z Bao, U Baumgarten, K Bessho, ...
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