New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation Y Cao, T Sato, M Orshansky, D Sylvester, C Hu Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No …, 2000 | 717 | 2000 |
Semiconductor integrated circuit S Matsui, T Sato, K Sakata, T Yaguchi, K Kuwabara, A Nakamura, ... US Patent 7,412,616, 2008 | 131 | 2008 |
Predictive technology model YU Cao, T Sato, D Sylvester, M Orshansky, C Hu Internet: http://ptm. asu. edu, 2002 | 118 | 2002 |
Data transmitter T Sato, Y Nishio, Y Nakagome US Patent 6,359,815, 2002 | 93 | 2002 |
Compact modeling of statistical BTI under trapping/detrapping JB Velamala, KB Sutaria, H Shimizu, H Awano, T Sato, G Wirth, Y Cao IEEE Transactions on Electron Devices 60 (11), 3645-3654, 2013 | 87 | 2013 |
Sequential importance sampling for low-probability and high-dimensional SRAM yield analysis K Katayama, S Hagiwara, H Tsutsui, H Ochi, T Sato 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 703-708, 2010 | 78 | 2010 |
Physics matters: statistical aging prediction under trapping/detrapping JB Velamala, K Sutaria, T Sato, Y Cao Proceedings of the 49th Annual Design Automation Conference, 139-144, 2012 | 66 | 2012 |
On-chip thermal gradient analysis and temperature flattening for SoC design T Sato, J Ichimiya, N Ono, K Hachiya, M Hashimoto Proceedings of the 2005 Asia and South Pacific Design Automation Conference …, 2005 | 63 | 2005 |
Modeling the overshooting effect for CMOS inverter delay analysis in nanometer technologies Z Huang, A Kurokawa, M Hashimoto, T Sato, M Jiang, Y Inoue IEEE transactions on computer-aided design of integrated circuits and …, 2010 | 59 | 2010 |
Circuit design for reliability R Reis, Y Cao, G Wirth Springer New York, 2015 | 55 | 2015 |
Aging statistics based on trapping/detrapping: Silicon evidence, modeling and long-term prediction JB Velamala, KB Sutaria, T Sato, Y Cao 2012 IEEE International Reliability Physics Symposium (IRPS), 2F. 2.1-2F. 2.5, 2012 | 53 | 2012 |
Efficient generation of delay change curves for noise-aware static timing analysis K Agarwal, Y Cao, T Sato, D Sylvester, C Hu Proceedings of the 2002 Asia and South Pacific Design Automation Conference, 77, 2002 | 45 | 2002 |
PARHELIA: Particle filter-based heart rate estimation from photoplethysmographic signals during physical exercise Y Fujita, M Hiromoto, T Sato IEEE Transactions on Biomedical Engineering 65 (1), 189-198, 2017 | 43 | 2017 |
Bidirectional closed-form transformation between on-chip coupling noise waveforms and interconnect delay-change curves T Sato, Y Cao, K Agarwal, D Sylvester, C Hu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2003 | 40 | 2003 |
Validation of a full-chip simulation model for supply noise and delay dependence on average voltage drop with on-chip delay measurement Y Ogasahara, T Enami, M Hashimoto, T Sato, T Onoye IEEE Transactions on Circuits and Systems II: Express Briefs 54 (10), 868-872, 2007 | 38 | 2007 |
Accurate in situ measurement of peak noise and delay change induced by interconnect coupling T Sato, D Sylvester, Y Cao, C Hu IEEE Journal of Solid-State Circuits 36 (10), 1587-1591, 2001 | 35 | 2001 |
Coin Flipping PUF: A Novel PUF With Improved Resistance Against Machine Learning Attacks Y Tanaka, S Bian, M Hiromoto, T Sato IEEE Transactions on Circuits and Systems II: Express Briefs 65 (5), 602-606, 2018 | 34 | 2018 |
A device array for efficient bias-temperature instability measurements T Sato, T Kozaki, T Uezono, H Tsutsui, H Ochi 2011 Proceedings of the European Solid-State Device Research Conference …, 2011 | 34 | 2011 |
Timing analysis considering temporal supply voltage fluctuation M Hashimoto, J Yamaguchi, T Sato, H Onodera Proceedings of the 2005 Asia and South Pacific Design Automation Conference …, 2005 | 34 | 2005 |
Aging statistics based on trapping/detrapping: Compact modeling and silicon validation KB Sutaria, JB Velamala, CH Kim, T Sato, Y Cao IEEE Transactions on Device and Materials Reliability 14 (2), 607-615, 2014 | 31 | 2014 |