| The Rocket Chip Generator K Asanovic, R Avizienis, J Bachrach, S Beamer, D Biancolin, C Celio, ... EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2016-17, 2016 | 871 | 2016 |
| Network requirements for resource disaggregation PX Gao, A Narayan, S Karandikar, J Carreira, S Han, R Agarwal, ... 12th USENIX Symposium on Operating Systems Design and Implementation (OSDI …, 2016 | 455 | 2016 |
| FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud S Karandikar, H Mao, D Kim, D Biancolin, A Amid, D Lee, N Pemberton, ... 45th International Symposium on Computer Architecture (ISCA 2018), 2018 | 327 | 2018 |
| Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs A Amid, D Biancolin, A Gonzalez, D Grubb, S Karandikar, H Liew, ... IEEE Micro 40 (4), 10-21, 2020 | 296 | 2020 |
| BOSS: Building Operating System Services. S Dawson-Haggerty, A Krioukov, J Taneja, S Karandikar, G Fierro, ... NSDI 13, 443-458, 2013 | 192 | 2013 |
| The rocket chip generator. EECS Department K Asanovic, R Avizienis, J Bachrach, S Beamer, D Biancolin, C Celio, ... University of California, Berkeley, Tech. Rep. UCB/EECS-2016-17, 2016 | 157 | 2016 |
| A Hardware Accelerator for Protocol Buffers S Karandikar, C Leary, C Kennelly, J Zhao, D Parimi, B Nikolic, ... MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture …, 2021 | 54 | 2021 |
| FPGA Accelerated INDEL Realignment in the Cloud L Wu, D Bruns-Smith, FA Nothaft, Q Huang, S Karandikar, J Le, A Lin, ... 2019 IEEE International Symposium on High Performance Computer Architecture …, 2019 | 51* | 2019 |
| FASED: FPGA-accelerated simulation and evaluation of DRAM D Biancolin, S Karandikar, D Kim, J Koenig, A Waterman, J Bachrach, ... Proceedings of the 2019 ACM/SIGDA International Symposium on Field …, 2019 | 42 | 2019 |
| FirePerf: FPGA-Accelerated Full-System Hardware/Software Performance Profiling and Co-Design S Karandikar, A Ou, A Amid, H Mao, R Katz, B Nikolić, K Asanović 25th International Conference on Architectural Support for Programming …, 2020 | 35 | 2020 |
| DESSERT: Debugging RTL Effectively with State Snapshotting for Error Replays across Trillions of cycles D Kim, C Celio, S Karandikar, D Biancolin, J Bachrach, K Asanović 2018 28th International Conference on Field Programmable Logic and …, 2018 | 30 | 2018 |
| The Hwacha Microarchitecture Manual, Version 3.8. Y Lee, A Ou, C Schmidt, S Karandikar, H Mao, K Asanovic EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS …, 2015 | 25* | 2015 |
| Vector Processors for Energy-Efficient Embedded Systems D Dabbelt, C Schmidt, E Love, H Mao, S Karandikar, K Asanovic Proceedings of the Third ACM International Workshop on Many-core Embedded …, 2016 | 24 | 2016 |
| Centrifuge: Evaluating full-system HLS-generated heterogenous-accelerator SoCs using FPGA-Acceleration Q Huang, C Yarp, S Karandikar, N Pemberton, B Brock, L Ma, G Dai, ... 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019 | 20 | 2019 |
| The rocket chip generator A Krste, A Rimas, B Jonathan, B Scott, B David, C Christopher, C Henry, ... EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS …, 2016 | 19* | 2016 |
| CDPU: Co-designing Compression and Decompression Processing Units for Hyperscale Systems S Karandikar, AN Udipi, J Choi, J Whangbo, J Zhao, S Kanev, E Lim, ... Proceedings of the 50th Annual International Symposium on Computer …, 2023 | 17* | 2023 |
| Profiling Hyperscale Big Data Processing A Gonzalez, A Kolli, S Khan, S Liu, V Dadu, S Karandikar, J Chang, ... Proceedings of the 50th Annual International Symposium on Computer …, 2023 | 14 | 2023 |
| Chipyard-An Integrated SoC Research and Implementation Environment A Amid, D Biancolin, A Gonzalez, D Grubb, S Karandikar, H Liew, ... 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 11* | 2020 |
| Hwacha Preliminary Evaluation Results, Version 3.8. Y Lee, C Schmidt, S Karandikar, D Dabbelt, A Ou, K Asanovic EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS …, 2015 | 10* | 2015 |
| Accessible, FPGA Resource-Optimized Simulation of Multiclock Systems in FireSim D Biancolin, A Magyar, S Karandikar, A Amid, B Nikolić, J Bachrach, ... IEEE Micro 41 (4), 58-66, 2021 | 6 | 2021 |
Krste AsanovicUC BerkeleyVerified email at berkeley.edu
