| Hierarchical test generation using precomputed tests for modules BT Murray, JP Hayes IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1990 | 296 | 1990 |
| Low-cost on-line fault detection using control flow assertions R Venkatasubramanian, JP Hayes, BT Murray 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003., 137-143, 2003 | 206 | 2003 |
| Testing ICs: Getting to the core of the problem BT Murray, JP Hayes Computer 29 (11), 32-38, 1996 | 125 | 1996 |
| Online BIST for embedded systems H Al-Asaad, BT Murray, JP Hayes IEEE design & Test of Computers 15 (4), 17-24, 1998 | 119 | 1998 |
| Transparent recovery from intermittent faults in time-triggered distributed systems N Kandasamy, JP Hayes, BT Murray IEEE Transactions on Computers 52 (2), 113-125, 2003 | 100 | 2003 |
| Built-in self testing of sequential circuits using precomputed test sets V Iyengar, K Chakrabarty, BT Murray Proceedings. 16th IEEE VLSI Test Symposium (Cat. No. 98TB100231), 418-423, 1998 | 97 | 1998 |
| Multi-module control-by-wire architecture BT Murray, JG D'ambrosio, SA Millsap, MD Byers, RJ Disser, JA Heinrichs, ... US Patent 6,424,900, 2002 | 96 | 2002 |
| Built-in test pattern generation for high-performance circuits using twisted-ring counters K Chakrabarty, BT Murray, V Iyengar Proceedings 17th IEEE VLSI Test Symposium (Cat. No. PR00146), 22-27, 1999 | 78 | 1999 |
| A system-safety process for by-wire automotive systems S Amberkar, JG D'Ambrosio, BT Murray, J Wysocki, BJ Czerny SAE transactions, 348-353, 2000 | 73 | 2000 |
| Deterministic built-in pattern generation for sequential circuits V Iyengar, K Chakrabarty, BT Murray Journal of Electronic Testing 15, 97-114, 1999 | 66 | 1999 |
| Optimal zero-aliasing space compaction of test responses K Chakrabarty, BT Murray, JP Hayes IEEE Transactions on Computers 47 (11), 1171-1187, 1998 | 65 | 1998 |
| Alzheimer’s protective A2T mutation changes the conformational landscape of the Aβ1–42 monomer differently than does the A2V mutation P Das, B Murray, G Belfort Biophysical Journal 108 (3), 738-747, 2015 | 62 | 2015 |
| Circuit with built-in test and method thereof BT Murray, K Chakrabarty, JP Hayes US Patent 5,790,562, 1998 | 60 | 1998 |
| Deterministic built-in test pattern generation for high-performance circuits using twisted-ring counters K Chakrabarty, BT Murray, V Iyengar IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8 (5), 633-636, 2000 | 56 | 2000 |
| Codesign of architectures for automotive powertrain modules X Hu, JG D'Ambrosio, BT Murray, DL Tang IEEE Micro 14 (4), 17-25, 1994 | 55 | 1994 |
| Dependable communication synthesis for distributed embedded systems N Kandasamy, JP Hayes, BT Murray International Conference on Computer Safety, Reliability, and Security, 275-288, 2003 | 54 | 2003 |
| Model-based fault detection and isolation system and method G Rizzoni, A Soliman, P Pisu, SS Amberkar, BT Murray US Patent 6,766,230, 2004 | 45 | 2004 |
| Design of built-in test generator circuits using width compression K Chakrabarty, BT Murray IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1998 | 45 | 1998 |
| Development experience with steer-by-wire T Kaufmann, S Millsap, B Murray, J Petrowski SAE transactions, 583-590, 2001 | 43 | 2001 |
| A2T and A2V A β peptides exhibit different aggregation kinetics, primary nucleation, morphology, structure, and LTP inhibition B Murray, M Sorci, J Rosenthal, J Lippens, D Isaacson, P Das, D Fabris, ... Proteins: Structure, Function, and Bioinformatics 84 (4), 488-500, 2016 | 42 | 2016 |
