Follow
Bastien Giraud
Bastien Giraud
IC Design Research Engineer, cea
Verified email at cea.fr
Title
Cited by
Cited by
Year
Resistive memories for ultra-low-power embedded computing design
E Vianello, O Thomas, G Molas, O Turkyilmaz, N Jovanovic, D Garbin, ...
2014 IEEE International Electron Devices Meeting 6, 1-6.3, 2014
1092014
Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology
P Flatresse, B Giraud, JP Noel, B Pelloux-Prayer, F Giner, DK Arora, ...
2013 IEEE International Solid-State Circuits Conference Digest of Technical†…, 2013
862013
Demonstration of BEOL-compatible ferroelectric Hf0.5Zr0.5O2 scaled FeRAM co-integrated with 130nm CMOS for embedded NVM applications
T Francois, L Grenouillet, J Coignus, P Blaise, C Carabasse, N Vaxelaire, ...
2019 IEEE International Electron Devices Meeting (IEDM), 15.7. 1-15.7. 4, 2019
812019
Experimental investigation of 4-kb RRAM arrays programming conditions suitable for TCAM
A Grossi, E Vianello, C Zambelli, P Royer, JP Noel, B Giraud, L Perniola, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (12†…, 2018
682018
UTBB FDSOI transistors with dual STI for a multi-Vt strategy at 20nm node and below
L Grenouillet, M Vinet, J Gimbert, B Giraud, JP Noel, Q Liu, P Khare, ...
2012 International Electron Devices Meeting, 3.6. 1-3.6. 4, 2012
632012
A 460 mhz at 397 mv, 2.6 ghz at 1.3 v, 32 bits vliw dsp embedding f max tracking
E Beigne, A Valentian, I Miro-Panades, R Wilson, P Flatresse, F Abouzeid, ...
IEEE Journal of Solid-State Circuits 50 (1), 125-136, 2014
592014
A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking
R Wilson, E Beigne, P Flatresse, A Valentian, F Abouzeid, T Benoist, ...
2014 IEEE International Solid-State Circuits Conference Digest of Technical†…, 2014
512014
DRC2: Dynamically Reconfigurable Computing Circuit based on memory architecture
KC Akyel, HP Charles, J Mottin, B Giraud, G Suraci, S Thuries, JP Noel
2016 IEEE International Conference on Rebooting Computing (ICRC), 1-8, 2016
472016
Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs
E Beignť, A Valentian, B Giraud, O Thomas, T Benoist, Y Thonnart, ...
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 613-618, 2013
392013
SneakPath compensation circuit for programming and read operations in RRAM-based CrossPoint architectures
A Levisse, B Giraud, JP NoŽl, M Moreau, JM Portal
2015 15th Non-Volatile Memory Technology Symposium (NVMTS), 1-4, 2015
322015
Fine grain multi-VTco-integration methodology in UTBB FD-SOI technology
B Pelloux-Prayer, A Valentian, B Giraud, Y Thonnart, JP Noel, P Flatresse, ...
2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration†…, 2013
302013
Design and simulation of a 128 kb embedded nonvolatile memory based on a hybrid RRAM (HfO2)/28 nm FDSOI CMOS technology
JM Portal, M Bocquet, S Onkaraiah, M Moreau, H Aziza, D Deleruyelle, ...
IEEE Transactions on Nanotechnology 16 (4), 677-686, 2017
292017
A comparative study of 6T and 4T SRAM cells in double-gate CMOS with statistical variation
B Giraud, A Amara, A Vladimirescu
2007 IEEE International Symposium on Circuits and Systems, 3022-3025, 2007
282007
Technology variability from a design perspective
B Nikolic, JH Park, J Kwak, B Giraud, Z Guo, LT Pang, SO Toh, R Jevtic, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 58 (9), 1996-2009, 2011
262011
In-depth characterization of resistive memory-based ternary content addressable memories
DRB Ly, B Giraud, JP NoŽl, A Grossi, N Castellani, G Sassine, JF Nodin, ...
2018 IEEE International Electron Devices Meeting (IEDM), 20.3. 1-20.3. 4, 2018
232018
Novel 1T2R1T RRAM-based ternary content addressable memory for large scale pattern recognition
DRB Ly, JP Noel, B Giraud, P Royer, E Esmanhotto, N Castellani, ...
2019 IEEE International Electron Devices Meeting (IEDM), 35.5. 1-35.5. 4, 2019
222019
Smart instruction codes for in-memory computing architectures compatible with standard SRAM interfaces
M Kooli, HP Charles, C Touzet, B Giraud, JP Noel
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE†…, 2018
222018
High-density 4T SRAM bitcell in 14-nm 3-D CoolCube technology exploiting assist techniques
R Boumchedda, JP Noel, B Giraud, KC Akyel, M Brocard, D Turgis, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (8†…, 2017
222017
16kbit HfO2:Si-based 1T-1C FeRAM Arrays Demonstrating High Performance Operation and Solder Reflow Compatibility
T Francois, J Coignus, A Makosiej, B Giraud, C Carabasse, J Barbot, ...
2021 IEEE International Electron Devices Meeting (IEDM), 33.1. 1-33.1. 4, 2021
202021
Design technology co-optimization of 3D-monolithic standard cells and SRAM exploiting dynamic back-bias for ultra-low-voltage operation
F Andrieu, R Berthelon, R Boumchedda, G Tricaud, L Brunet, P Batude, ...
2017 IEEE International Electron Devices Meeting (IEDM), 20.3. 1-20.3. 4, 2017
202017
The system can't perform the operation now. Try again later.
Articles 1–20